原代码：

module jiecheng(
Reset,
Start,
Clk,
Data,
Done,
Result,
Exponent
);
input Reset,Start,Clk;
input[4:0] Data;

output Done;
reg Done;
output[7:0] Result,Exponent;
reg[7:0] Result,Exponent;

reg[4:0]InLatch;

always@(posedge Clk)
begin:BLOCK_A
integer NextResult,J;

if((Start&&Done)||Reset)
begin
Result<='b1;
Exponent<='b0;
InLatch<=Data;
Done<='b0;
end
else
begin
if((InLatch>1)&&(!Done))
begin
NextResult=Result*InLatch;
InLatch<=InLatch-1;
end
else
NextResult=Result;
if(InLatch<=1)
Done<='b1;
for(J=1;J<=5;J=J+1)
begin
if(NextResult>256)
begin
NextResult=NextResult>>1;
Exponent<=Exponent+1;
end
end
Result<=NextResult;
end
end
endmodule

改进后：

module jiecheng(
Reset,
Clk,
Data,
Done,
Result,
Exponent
);
input Reset,Clk;
input[4:0] Data;

output Done;
reg Done;
output[7:0] Result,Exponent;
reg[7:0] Result,Exponent;

reg unsigned [4:0]InLatch;

always@(posedge Clk)
begin:BLOCK_A
integer NextResult,J;

if(Reset)
begin
Result<='b1;
Exponent<='b0;
InLatch<=Data;
Done<='b0;
end
else
begin
if(InLatch>1)
InLatch<=InLatch-1;
if(InLatch==1)
Done<='b1;
NextResult=Result*InLatch; //此处综合为组合逻辑，在quartus 2c70芯片中被综合为一个硬件乘法器
for(J=1;J<=5;J=J+1) //此for循环被综合为组合逻辑，根据NextResult的值，在Exponent的基础之上
begin //一个数值，并且得到一个新的NextResult这个NextResult是乘法器输出

if(NextResult>256) //NextResult对256取模后的结果
begin
NextResult=NextResult>>1;//"="左边的NextResult和右边的NextResult已经是不同的信号线虽然名字相同
Exponent<=Exponent+1;
end
end
Result<=NextResult;
end
end
endmodule

MSN空间完美搬家到新浪博客!